Wireless communication devices have become ubiquitous in today's society. Such devices employ a wide variety of integrated circuits (ICs) to support a wide variety of wireless communication standards. These wireless communications standards include Global Systems for Mobile Communication (GSM), Wideband Code Division Multiple Access (WCDMA), and Code Division Multiple Access 2000 (CDMA2K) to name a few. The wireless device may be configured to support the various wireless communication standards.
Wireless communication devices have traditionally implemented separate analog circuitry for each wireless communication standard that was supported by the wireless device. For instance, one analog receive path would be dedicated to GSM, a separate analog receive path would be dedicated to WCDMA, another analog receive path would be dedicated to CDMA2K, and yet other analog receive paths would be dedicated to other wireless communication standards. Supporting multiple communication standards in this manner often requires duplicate circuitry for each channel, where each copy of the circuitry is tuned to support different frequency ranges. Such an approach is undesirable for several reasons, especially in the context of portable wireless devices such as cell phones. First, the duplicate circuitry consumes additional battery power, which is a primary concern in portable wireless devices. Second, the duplicate circuitry utilizes additional space within the often-confined space of the portable wireless device. Lastly, once analog circuitry has been configured to support a particular wireless communication standard, the analog circuitry is difficult to reconfigure to support a different communication standard.
Modern integrated circuits (ICs) integrate DSP functionality and analog functionality on the same IC, thereby allowing multiple communication standards to be supported by a single IC. FIG. 1 depicts a direct conversion receiver 10 capable of supporting multiple communication standards. Radio frequency (RF) signals are received by antenna 12 and amplified by a low noise amplifier (LNA) 14. The output of the LNA 14 is provided to an in-phase mixer 16 and to a quadrature mixer 18. A local oscillator (LO) provides a signal to a quadrature signal generator 20. Quadrature signal generator 20 provides the LO signal to mixer 16 and a quadrature version of the LO signal to mixer 18. In this manner, the RF signals may be directly “down-converted” or brought down to the lower frequency baseband signal range without first down converting to an intermediate frequency (IF).
The magnitude of the signal received from antenna 12 varies based upon the distance between system 10 and the transmitter; this variation is sometimes referred to as “dynamic range”. In the case of a cellular base station, if a cell phone is close to the base station then the signal strength is large whereas if the cell phone is far away from the base station then the signal strength is weak. In practice, the dynamic range may be on the order of 100 dB or a ratio of 100,000:1.
In order to accommodate such a large dynamic range, variable gain amplifiers (VGAs) 22-25 amplify or attenuate mixed signals from mixers 16 and 18. As well as amplifying desired signals, amplifiers 22-24 also amplify undesired signals. Low pass filters (LPFs) 26 and 28 block undesired signal frequencies. Analog to digital converters (ADCs) 30 and 32 convert the analog baseband signal into a digital signal for further signal processing by digital filters 34 and 36 and digital baseband processor 37. Processor 37 may decode the digital signal according to one of the many supported wireless communications standards.
ADCs 30 and 32 have a range of analog values (both in terms of frequency and magnitude) that they are capable of converting to a digital value. Analog values that are above the upper limit of the magnitude range may saturate the ADC. The VGAs 22-25 strive (under the control of the processor 37) to keep the input to ADCs 30 and 32 within a desired range of analog values that ADCs 30 and 32 are capable of converting to digital values without saturation. ADCs 30 and 32 are driven by a sample clock of frequency Fs. If the sample clock frequency Fs is not more than twice the maximum frequency of the sampled signal (a limit known as the Nyquist frequency), then ADCs 30 and 32 will undesirably generate aliased versions of the converted signals. Accordingly, the LPF 26 and 28 may be designed to limit the signal spectrum to less than half the Nyquist frequency. Alternatively, anti-alias filters may be implemented before ADCs 30 and 32 to limit the frequency range of the sampled analog signal to less than half the Nyquist frequency, thus minimizing the interference introduced by the aliased signals on the desired signal.
Although receiver 10 overcomes some of the disadvantages of the analog signal processing systems mentioned above, it too has drawbacks. First, although processor 37 dynamically adjusts to the various communications standards, dynamically configuring the analog blocks, such as LPFs 26 and 28 and the anti-alias filters, is difficult due to the different filtering and noise requirements of each communication standard. Second, LPFs 26 and 28 as well as the anti-alias filters are integrated on the same die as the other components of system 10, and since LPFs 26 and 28 and the anti-alias filters accommodate multiple communication standards, they may consume a large proportion of the total die size. Indeed, it is not uncommon for a die with a total area of 3 to 4 mm2 to contain a programmable filter that consumes 2 mm2. Third, matching the analog circuitry along the in-phase and quadrature paths can be difficult, particularly when this analog circuitry supports multiple communications standards. Accordingly, a receiver architecture capable of implementing multiple communications standards more efficiently is desirable.